1. Field of the Invention
The present invention relates to testing of equipment used in semiconductor manufacturing, and more particularly, to testing of probe cards that are used to probe semiconductor wafers.
2. Related Art
Semiconductor dies must be tested during the manufacturing process to insure the reliability and performance characteristics of the integrated circuits on the dies. Accordingly, different testing procedures have been developed by semiconductor manufacturers for testing semiconductor dies. Standard tests for gross functionality are typically performed by probe testing the dies at the wafer level. Probe testing at the wafer level can also be used to rate the speed grades of the dies.
Testing a large number of integrated circuit chips in parallel at the wafer level provides a significant advantage since test time and cost are substantially reduced. At present, large scale testers including mainframe computers are needed to test even one chip at a time, and the complexity of these machines is increased when the capability of testing arrays of chips in parallel is added. Nevertheless, because of the time savings parallel testing provides, high pin-count testers capable of probing and collecting data from many chips simultaneously have been introduced, and the number of chips that can be tested simultaneously has been gradually increasing.
An important element of the testing apparatus is a probe card, which includes a number of probes that in turn connect to the wafer under test during the testing process. Ensuring that the probe card is itself functioning properly is therefore an important part of the testing process.